The present invention relates generally to integrated circuit (IC) designs, and more particularly to a power up/down sequence scheme for memory devices.
A memory device is usually implemented with a power down scheme that cuts off power supply to certain circuit modules when certain modes, such as the sleep mode or the standby mode, are activated in order to reduce the power consumption. A typical power down scheme utilizes an internal power control circuit, a power supply switch (VDD switch), and a ground voltage switch (VSS switch). FIG. 1 schematically illustrates the internal power control circuit 100, the VSS switch 130 and the VDD switch 160 that are needed for a typical power down scheme. The internal power control circuit 100 is comprised of an inverter 102 with its output terminal coupled to an input terminal of an inverter 104 and to an input terminal of an inverter 106. The inverter 102 is connected to an external power supply VDD, an external ground voltage VSS, and an internal ground voltage VSSI. The inverter 104 is connected to an external power supply VDD, an internal power supply VDDI, and the external ground voltage VSS. The inverter 106 is also connected to an external power supply VDD, an internal power supply VDDI, and the external ground voltage VSS. The output terminals of the inverters 104 and 106 are coupled to word lines WLR and WL, respectively. A PMOS transistor 108 is connected to the external power supply VDD at its source, and to a node 110, which is coupled to the output terminal of the inverter 102 and the input terminals of the inverters 104 and 106, at its drain. The gate of the PMOS transistor 108 is controlled by a power down signal (PD).
The VDD switch 160 is comprised of PMOS transistors 162 and 164 coupled between the external power supply VDD and the internal power supply VDDI. The gate of the PMOS transistor 162 is controlled by the first power supply switch control signal PDL, and the gate of the PMOS transistor 164 is controlled by the second power supply switch control signal PDR. The VSS switch 130 contains an NMOS transistor 132 coupled between the external ground voltage VSS and the internal ground voltage VSSI. The gate of the NMOS transistor 132 is controlled by the power down signal PD.
When a power down process is activated, the power down signal PD is pulled down to turn on the PMOS transistor 108 to pass the external power supply VDD to the input terminals of the inverters 104 and 106. As a result, the voltages on word lines WL and WLR are kept at a low level, and therefore maintain the data stored in a memory array (not shown in the figure) undisturbed by the power changes in peripheral circuits. The low power down signal PD turns off the NMOS transistor 132, and therefore isolating the external ground voltage VSS from the internal ground voltage VSSI. During the power down process, the first power supply switch control signal PDL and the second power supply switch control signal PDR are pulled to a high level to turn off the PMOS transistors 162 and 164, such that the external power supply VDD and the internal power supply VDDI are isolated from each other.
One drawback of the conventional power down scheme is the data glitch caused by the inappropriate timing of controlling the PMOS transistor 108, the VDD switch 160, and the VSS switch 130. During the power down process, the power down signal PD is pulled low, and the power supply switch control signals PDL and PDR are pulled high at the same time. The current path between the external power supply VDD and VDDI may be completely cut off before the PMOS transistor 108 is fully turn on. As a result, the VDDI line connected to the inverters 104 and 106 may be floating. This may cause the signals on the word lines WL and WLR to glitch, and therefore disturb the data stored in the memory array.
What is needed is power up/down scheme for peripheral circuits that does not disturb the data stored in memory arrays.